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Rev 1; 1/09
Cache-Memory Battery-Backup Management IC
General Description
The DS2731 is a complete power-management solution for modular backup applications. It is well-suited for 2.5V and below memory bus voltages, with an input voltage of 12V. The DS2731 includes an internal MOSFET switching power stage for charging a one-cell lithium chemistry battery. It has a fully integrated synchronous buck regulator capable of supplying up to 450mA of cache backup supply current, and the necessary logic and power devices for handling the switchover from system power to battery power. The battery charging method of the DS2731 is constant current/constant voltage (CCCV). Output voltage can be margined from 3.8V to 4.6V using a resistordivider. Charge is terminated when the charging current falls below 5% of full charge current. Switchover to battery backup is initiated by an internal comparator and occurs automatically when a sensed-input voltage drops below 2.93V. At light loads, the 2MHz internal synchronous buck regulator operates in burst mode for maximum efficiency. All nonessential functions of the DS2731 are disabled while supplying holdup current to the cache memory, and the IC goes into very low-current dormant mode when the battery voltage drops below a user-settable threshold. The DS2731 keeps track of charge status and signals the user through open-drain I/O pins that can be used to drive LEDs. o Lithium Chemistry CCCV Charger o Adjustable Regulated Charging Up to 1.5A DC o Adjustable Charge Voltage from 3.8V to 4.6V o External and Internal Thermal Protection o Safety Timer Secondary Termination o LED Indicator Outputs o Detects Power Outage and Switches Between Normal Power and Backup Battery o Adjustable High-Efficiency Synchronous Buck Regulator with Skip Mode at Light Loads o Low-Power Consumption in Discharge Mode
Features
DS2731
Ordering Information
PART DS2731E+ TEMP RANGE -20C to +70C PINPACKAGE 28 TSSOP-EP* (173 mils) 28 TSSOP-EP* (173 mils) TOP MARK DS2731 DS2731
DS2731E+T&R -20C to +70C
Applications
RAID Controller Card
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
Typical Operating Circuit
TOP VIEW +
MARGIN STMR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 *EP
Pin Configuration
28 27 26 25 24 23 22
THM RSET BATT+ SNS CGATE VIN CHG1 CHG2 CGND1 CGND2 CHARGE FAULT DONE ENC
DS2731
MAIN POWER SWITCH MODE CHARGER (CCCV)
CTG AUX CBIAS
LITHIUM BACKUP CELL
VREG CIN LX SGND AGND REF LO_BATT
DS2731
21 20 19 18 17 16 15
AUXILIARY POWER
POWER MANAGEMENT
SWITCHING REGULATOR
CACHE MEMORY
DIV ENS
TSSOP
*EXPOSED PAD
________________________________________________________________ Maxim Integrated Products
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Cache-Memory Battery-Backup Management IC DS2731
ABSOLUTE MAXIMUM RATINGS
Voltage Range on CGND1, CGND2, and SGND Pins Relative to AGND ...........................-0.3V to +0.3V Voltage Range on VIN, CHG1, CHG2, and CGATE Pins Relative to AGND........................-0.3V to +16.0V Voltage Range on CHARGE, FAULT, and DONE Pins Relative to AGND .........................-0.3V to +16.0V Voltage Range on Any Other Pin Relative to AGND ............................................................-0.3V to +6.0V Continuous Sink Current on VIN, CGND1, CGND2, SGND, AUX, BATT+ Pins ......................750mA each Continuous Source Current on CHG1, CHG2, and LX Pins ..............................................750mA each Continuous Sink Current on CHARGE, FAULT, and DONE Pins .........................................20mA each Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(VIN = +10.8V to +13.2V, TA = -20C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Charger Supply Voltage Auxiliary Supply Voltage Battery Voltage LED Voltage (CHARGE, FAULT, DONE Pins) Charger Enable (ENC) Switcher Enable (ENS) SYMBOL VIN VAUX VBATT+ (Note 1) (Note 1) Operating as input (Note 1) (Note 1) (Notes 1, 2) (Notes 1, 2) CONDITIONS MIN 10.8 3.0 2.7 0 0 0 TYP 12.0 MAX 13.2 3.6 5.0 VIN + 0.3 VCBIAS + 0.3 VCIN + 0.3 UNITS V V V V V V
CHARGER CIRCUIT ELECTRICAL CHARACTERISTICS
(VIN = +10.8V to +13.2V, TA = -20C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Charger Idle Supply Current SYMBOL I IN IAUX Regulator Supply Current (Note 3) IBATT+ I SLEEP CBIAS Regulator Voltage C GATE Regulator Voltage C GATE Capacitance CBIAS Capacitance Enable Logic-Low (ENS, ENC) Enable Logic-High (ENS, ENC) VCBIAS VCGATE CCGATE CCBIAS VIL VIH (Notes 4, 5) (Notes 5, 6) 1.6 2.2 0.22 0.4 CONDITIONS VIN > VUVLO-CHG (Note 3), VAUX = 3.3V VAUX > VTRIP VAUX < VTRIP, VBATT+ > VSLEEP, ENS disabled VIN = VAUX = 0.0V, VBATT+ < VSLEEP 3.3 VIN - 4.0 MIN TYP 1 100 100 150 10 MAX UNITS mA A A A V V F F V V
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Cache-Memory Battery-Backup Management IC
CHARGER CIRCUIT ELECTRICAL CHARACTERISTICS (continued)
(VIN = +10.8V to +13.2V, TA = -20C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Enable Hysteresis (ENS, ENC) Pulldown Resistance (ENS, ENC) LED Outputs Low (CHARGE, DONE, FAULT) Fault LED Flash Rate Preconditioning Charge Threshold Preconditioning Hysteresis Preconditioning Charge Current Precondition Timeout Charge-Current Range (RSET Resistance) Charge-Current Accuracy Overcurrent Clamp Constant-Voltage Threshold Range MARGIN Pin Leakage Constant-Voltage Charge Accuracy Charge Termination (CV) Current Charge-Restart Threshold Safety Timeout Range (STMR Resistance) Safety Timeout Error Battery Charger Switching Period Charger Undervoltage Lockout High-Side MOSFET On-Resistance SYMBOL VHYS-EN RPD VOL fFAULT VMIN VHYS IPRE t PRE ICHG I ERR-CHG Charge current determined by RSET (Note 7) RSET resistor tolerance 0.1%, RSNS = 0.050 Charge voltage determined by MARGIN pin voltage VBATT+ < VMIN (Note 1) 2.55 50 5.0 27 0.5 5.0 -5 1.7 3.6 -2 -25.0 4.0 94 1 22 -5 0.83 8 ICHG = 1A, VIN = 10.8V (Note 10) ICHG = 1A, VIN = 10.8V (Note 10) VIN = 0V, VCV = 4.2V, ENC = 0V VIN = 12V, VCV = 4.2V, ENC = 0V No charge current, VIN = 12V Using typical application components -2 1 1.00 10 0.4 0.15 10 10 +2 A A A ms Full load (1.5A) (Note 9) 5.0 95 4.2 I OL = 10mA 4 2.60 100 10.0 30 15.0 33 1.5 1.6 +5 2.5 4.6 +2 +25.0 6.0 96 10 220 +5 2.70 CONDITIONS MIN 35 100 TYP 70 200 MAX 140 300 1.0 UNITS mV k V Hz V mV % of ICHG min A k % A V A mV % of ICHG % of VCV hr k % s V
DS2731
IOVERCURRENT RSET = 0 or RSNS = 0 VCV ILEAKAGE VERR-CV ITERMINATE In constant-voltage mode VDELTA t SAFETY tERR-SAFETY RSTMR = 22,000 t SW-CHG VUVLO-CHG RDSON-CP (Note 8)
Low-Side MOSFET On-Resistance RDSON-CN Reverse Leakage of Charge FET (CHG1, CHG2) Forward Leakage of Charge FET (CHG1, CHG2) SNS Leakage Current Startup Time IREVERSE IFORWARD ILKG-CHG t START
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Cache-Memory Battery-Backup Management IC DS2731
BUCK REGULATOR AND POWER MUX CIRCUIT ELECTRICAL CHARACTERISTICS
(VIN = +10.8V to +13.2V, TA = -20C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Auxiliary Input Trip Threshold Auxiliary Input Trip Hysteresis Multiplexer Delay Break-Before-Make Power Multiplexer On-Resistance Regulator Output Voltage Range DIV Pin Voltage Range Regulator Output Voltage Error Low-Battery Threshold Adjustment Range LO_BATT Pin Voltage Range VREF Voltage VREF Load Range (Equivalent Resistance) Buck Regulator Switching Period Regulator Undervoltage Lockout Switching Power pFET Resistance Switching Power nFET Resistance nFET Off Threshold Switching Power pFET Overcurrent Limit Switching Power nFET Overcurrent Limit VREG Pin Leakage SYMBOL VTRIP VHYS-TRIP tBREAK RMUX VREG VDIV VERR-REG VSLEEP VLO-BATT VREF IREF t SW-REG VUVLO-REG RDSON-SP RDSON-SN I OFFN I OCLP I OCLN ILKG-REG I OUT = 100mADC BATT+ = 3.0V, VAUX = 0 (Note 10) I OUT = 100mADC BATT+ = 3.0V, VAUX = 0 (Note 10) 0 500 400 -2 40 750 650 50mA (Note 9) 2.45 (Note 9) (Note 1) Relative to actual VTRIP Switching to/from BATT+ (Note 11) IMUX = 10mA, BATT+ or AUX source Set by VDIV pin voltage 0.9 0.4 -5.0 2.75 0.6 1.220 1.22 1000 500 2.70 0.6 1.2 80 1000 900 +2 mA mA mA A 1.238 0.6 CONDITIONS MIN 2.85 50 TYP 2.93 80 MAX 3.00 150 1 1.0 2.5 VREF +5.0 3.00 VREF 1.260 126.00 10 V V % V V V A k ns V UNITS V mV s
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Cache-Memory Battery-Backup Management IC
THERMAL PROTECTION CHARACTERISTICS
(VIN = +10.8V to +13.2V, TA = -20C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER THM Pin Internal Pullup Voltage THM Pin Internal Resistance Thermistor Overtemperature HALT Threshold Thermistor Overtemperature Resume Threshold Thermistor Undertemperature HALT Threshold Thermistor Undertemperature Resume Threshold Thermistor Disable Threshold Internal Overtemperature Protection Threshold CCCV Internal Overtemperature Hysteresis CCCV Internal Overtemperature Protection Threshold MEM_REG Internal Overtemperature Hysteresis MEM_REG Charging Current Reduction Threshold Charging Current Reduction Rate SYMBOL VTHM RTHM VHOT VHYS-HOT VCOLD VHYS-COLD VDISABLE T PROTECT_CCCV CONDITIONS (Notes 1, 12) THM to CBIAS (Note 12) (Notes 12, 13) (Notes 12, 13) (Notes 12, 13) (Notes 12, 13) (Notes 12, 13) (Note 12) 0.02 0.727 9.8 0.271 MIN TYP VCBIAS 10.0 0.283 0.3055 0.739 0.714 0.03 160 -20 165 -15 100 133 0.04 0.748 10.2 0.292 MAX UNITS V k Ratio to VCBIAS Ratio to VCBIAS Ratio to VCBIAS Ratio to VCBIAS Ratio to VCBIAS C C C C C mA/C
DS2731
THYS-PROTECT_CCCV (Note 12) T PROTECT_MEMREG THYS-PROTECT_
MEMREG
(Note 14) (Note 14) (Note 12) (Note 12)
TCHOKE TCHOKE_RATE
Note 1: Note 2: Note 3:
Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14:
All voltages referenced to AGND pin. VCIN is equivalent to VAUX when VAUX is greater than VTRIP, otherwise VCIN is equivalent to VBATT+. Supply-current specification is only for current drain of the IC and does not include cell-charge current, load-supply current, or any external resistor bias currents. The only exception is ISLEEP, which does account for complete current drain of the lithium cell during low-battery conditions. Below this voltage, the input is guaranteed to be logic-low. Operating from 3.3V 10%. Above this voltage, the input is guaranteed to be logic-high. Assumes an RSNS value of 0.05. Relative to VCV. With recommended application circuit. Includes complete package resistance. This specification is from the rising or falling edge of ENS to the closure of the switch and includes whatever delay is in the internal logic and FET drivers. Applies to charger. Multiply these values by CBIAS voltage to get value in volts. Recommended value of resistor in divider network is 10k 1%. Tolerance includes tolerances of internal resistance and CBIAS voltage. Applies to memory buck regulator.
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Cache-Memory Battery-Backup Management IC DS2731
R8 4.7k R7 4.7k R6 4.7k ISOLATED GROUND AREA CHARGE CHG1 FAULT 17 CHG2 FAULT SNS DONE 16 BATT+ DONE 25 26 SNS BATT+ C6 47F 22 21 CHG L2 6.8H R9 0.050 J1 1 BATTERY+
CLED Y FLED R DLED G J3 1 VIN J4 1 CGND J5 1 AUX+
CHARGE 18
VIN 23 C4 22F CGND C5 22F C7 10F
VIN CGND1 20 19 CGND CGND2 CGATE J2 1 BATTERY-
CGATE 24
AUX SYSTEM CONTROL ENC-RES SYSTEM CONTROL ENS-RES C1 10F J6 ENC 1
4
AUX
U1
C
DS2731
ENC 15 ENC THM 28 THM THMI 10k OR 103AT-2
ENS 14 1 J7 ENS CBIAS
ENS
5
CBIAS LO_BATT DIV REF MARGIN STMR CIN 7 CIN VREG LX 6 8 VREG LX J9 TEST 1
LO_BATT 12 C R3 590k R4 240k R5 360k DIV 13 REF 11 1 2
ISOLATED GROUND AREA L1 2.2H
MARGIN R1 56.2k R13 2.49k R2 10.2k STMR
J8 1 MEM+ C3 47F C2 47F J10 1 MEM-
RSET 27
RSET AGND 10
SGND CTG 3
9 S
Figure 1. Typical Application Diagram
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Cache-Memory Battery-Backup Management IC
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 -- NAME MARGIN STMR CTG AUX CBIAS VREG CIN LX SGND AGND REF LO_BATT DIV ENS ENC DONE FAULT CHARGE CGND2 CGND1 CHG2 CHG1 VIN CGATE SNS BATT+ RSET THM EP FUNCTION Voltage-Margining Input. Selects regulation voltage of charging circuit. Connect to the STMR pin through a resistor-divider. Voltage Safety-Timer Input. Sets timeout period for a charge cycle based on external resistance to AGND. Connect To Ground. Must be connected to AGND externally. Auxiliary. External supply input to switching supply. Connect to system 3.3V supply. Internal Regulator Output. Internal supply for the charging circuit generated from the VIN input. Bypass with a capacitor to AGND. Cache Voltage-Sense Input. Feedback for regulation of the switching circuit voltage. Connect to the positive side of the switching output load. Holdup/Bypass Capacitor. Internal supply for the switching regulator. Bypass with a 4.7F capacitor to AGND. Switching Node, Backup Supply. Output from the switching regulator. Connect to the switching regulator's external coil. Switcher Ground. Ground reference for the switching regulator. Connect to the negative side of the load. Analog Ground. Ground reference for the charging circuit. Connect to the negative side of the battery. Voltage Reference for Backup. 1.238V voltage reference used to set regulation voltage and low-batterydetection threshold. Connect to AGND through a resistor network. Low-Battery Detection. Selects the low-battery shutdown threshold of the switching regulator. Connect to the REF pin through a resistor-divider. Voltage Divider for Backup. Controls the voltage output level of the switching regulator. Connect to the REF pin through a resistor-divider. Enable Switcher. Active-low enable for the switching regulator. Enable Charger. Active-high enable for the charging circuit. Charge-Done Indicator. Open-drain active-low output indicating successful charge completion of the external cell. Charger-Fault Indicator. Open-drain active-low output indicating failure during charge of the external cell. Charge Indicator. Open-drain active-low output indicating charge of the external cell in progress. Charger Ground 2. Ground reference for battery-charging circuit. Connect to negative side of external cell. Charger Ground 1. Ground reference for battery-charging circuit. Connect to negative side of external cell. High-Current Charger Output 2. Output from the charging circuit. Connect to charging circuit's external coil. High-Current Charger Output 1. Output from the charging circuit. Connect to charging circuit's external coil. Charge-Supply Input. Connect to 10.8V to 13.2V system supply. Floating Gate Drive Bypass. Internal supply for the charger gate control. Bypass with a 2.2F capacitor to VIN. Current-Sense Input. Feedback for regulator of charger current. Connect a 0.050 between SNS and BATT+. sense resistor
DS2731
Battery Terminal Voltage. Feedback for regulation of charger voltage and supply to switching regulator during power loss. Charge-Setting Resistor Intput. Selects CC charge rate for external lithium cell. Connect to AGND through an external resistor. Thermistor Input. Connect to 10k NTC thermistor with good thermal contact to the external lithium cell. Exposed Paddle. It is recommended the exposed pad be connected to system ground.
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Cache-Memory Battery-Backup Management IC DS2731
CHG1 12V INPUT VIN GATE REGULATOR CGATE C STMR SAFETY TIMER PRECONDITION TIMER MARGIN INTERNAL THERMAL SENSE THM RSET 10k CBIAS ENC BATT+ 2.93V REFERENCE 0.3 0.6 AUX 3.3V INPUT BIAS REGULATOR I V SNS BATT+ 0.4 MAX GATE DRIVERS CHG2
CCCV CONTROLLER
0.15 MAX
CGND1
CGND2 C AGND CHARGE FAULT DONE
SUPPLY CONTROL 0.3 CIN
DS2731
OCLP 1.238V REFERENCE UVLO 2MHz PWM SWITCHING REGULATOR
C
REF
0.7 LX OCLN 1.0 1M 10pF VREG
DIV
LOAD
HYSTERESIS ENS LO_BATT BATT+
1M SGND 4.5:1 SCALER C S S
Figure 2. Block Diagram
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Cache-Memory Battery-Backup Management IC
Detailed Description
The DS2731 is a complete power-management solution for modular backup applications. It is well suited for 2.5V and below memory bus voltages. It has a 12V supply input for battery charging and a 3.3V aux supply input for power failure circuitry and memory voltage regulation. The DS2731 includes an internal MOSFETswitching power stage for charging a lithium-ion (Li+) cell. It has a fully integrated synchronous-buck regulator capable of supplying up to 450mA of cache-backup supply current. It also handles switching from system power to battery power. The battery-charging method is CCCV. Charging can be broken into three different modes: precondition, constant-current (CC) charge, and constant-voltage (CV) charge. Precondition mode charges at a reduced rate for a severely depleted cell. CC mode charge rate is user selectable from 0.5A to 1.5A. In CV mode, charge is terminated when the charging current falls below 5% of CC mode charge rate. The CV mode output is also user selectable from 3.8V to 4.6V. Charge status is signaled to the user through three open-drain pins that can be used to drive LEDs. A thermistor input is provided to prevent charging outside of temperature specifications and a safety timer prevents the continued charging of a damaged cell. Switchover to battery backup is initiated by an internal comparator and occurs automatically when a sensed input voltage drops below 2.93V. The power failure switching circuitry can be disabled by the user. Memory voltage is user selectable from 0.9V to 2.5V. At light loads, the 2MHz internal synchronous buck regulator operates in burst mode for maximum efficiency. All nonessential functions of the DS2731 are disabled during a power failure while supplying holdup current to the cache memory. To prevent damaging the battery, the regulator shuts down and the IC goes into a very low-current dormant mode when the battery voltage drops below a user-settable threshold (LO_BATT).
Li+ Charger
The CCCV charger circuitry is powered by the 12V input supply. When the charger circuitry is enabled, battery voltage is continuously monitored at the BATT+ pin. Charging begins when the battery voltage drops below the charge restart threshold. Accurate charge current measurements are achieved by the Kelvin remote-sense connections at the SNS and BATT+ pins. Measuring the voltage through a Kelvin remote-sense connection eliminates offset error caused by small trace resistances at high current.
DS2731
Charging Algorithm
From initiate, CC charging proceeds if ENC is high, the UVLO-CHG is false, the die temperature is below TPROTECT_CCCV, and the battery is above the minimum voltage. If the battery is below the minimum voltage, the charger goes into preconditioning charge. Once the battery voltage exceeds VMIN, the charger proceeds to CC mode. Precondition charge has a default 30-minute timer. If the timer expires before the battery voltage exceeds VMIN, the charger goes to fault. For CC charging, the charge safety timer starts. CC charging proceeds until the output voltage reaches the CV set point. The charger then proceeds to CV mode. Charging terminates when the current drops below 5% of the CC charge rate. The charge-safety timer duration is the sum of the CC and CV charge times and should be set to about 15% above the expected maximum charge time. If the charge-safety timer expires, the charger goes to fault. After charge termination, the charger monitors the battery voltage for self-discharge. When it drops 200mV below the CV charge threshold, the charger enters Initiate and a new charge cycle begins. Note: VAUX must be above 3.08V for the charger to operate.
Precharge Mode
Precharge mode is intended to restore severely depleted cells. Batteries with a voltage < VMIN charge at a reduced rate, 10% x ICHG, to prevent damaging the cell. Precharge mode has a fixed safety timer of 30 minutes. This timer is independent of the STMR pin. If the battery voltage has not exceeded VMIN within 30 minutes, the charger goes to the fault state. The charge pin is active during precharge mode.
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Cache-Memory Battery-Backup Management IC DS2731
ASYNCHRONOUS FROM ANY STATE ENC TRUE OR POWER-ON RESET (POR)
VBATT > VDIV INITIATE* DONE LED ACTIVE TIMERS RESET NO CURRENT FLOW VBATT+ < VMIN
VBATT+ < VDIV DONE DONE LED ACTIVE TIMERS RESET NO CURRENT FLOW
VBATT+ VMIN =
PRECONDITION CHARGE LED ACTIVE PRECONDITION TIMER ACTIVE CURRENT REGULATED TO IPRE
VBATT+ VMIN =
CONSTANT-CURRENT CHARGE CHARGE LED ACTIVE SAFETY TIMER ACTIVE CURRENT REGULATED BY RSET**
ISNS < ITERMINATE
ENC TOGGLED FALSE THEN TRUE OR POR PRECONDITION TIMEOUT
SAFETY TIMEOUT
VBATT+ VMARGIN =
FAULT FAULT LED ACTIVE, TIMERS INACTIVE, NO CURRENT FLOW SAFETY TIMER FAULT CONDITION TEMPERATURE FAULT CONDITION
CONSTANT-VOLTAGE CHARGE CHARGE LED ACTIVE SAFETY TIMER ACTIVE CURRENT REGULATED BY RMARGIN
SAFETY TIMEOUT
RETURN TO PREVIOUS STATE
TTHERMISTOR = THYS-HOT AND TTHERMISTOR = THYS-COLD AND TDS2731 = THYS-PROTECT
ASYNCHRONOUS FROM ANY STATE
TTHERMISTOR > THOT OR TTHERMISTOR < TCOLD OR TDS2731 > TPROTECT
*VIN > VUVLO-CHG, VAUX > 3.08V MUST EXIST BEFORE CHARGER OPERATES. **IF THE DS2731 DIE TEMPERATURE EXCEEDS TCHOKE, THE DS2731 BEGINS REDUCING CHARGE CURRENT BELOW THE RSET VALUE TO PROTECT THE IC.
Figure 3. Charger State Diagram
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Cache-Memory Battery-Backup Management IC DS2731
I PRECHARGE MODE CHARGE BEGIN CONSTANT-CURRENT MODE CONSTANT-VOLTAGE MODE CHARGE END VPK ICHARGE V
V I
10% x ICHARGE
VMIN 5% x ICHARGE
t CHARGE TERMINATION
Figure 4. Li+ Battery Charging Characteristics
Constant-Current (CC) Mode
CC mode is entered either directly from initiate or after precharge. Current is regulated based on the voltage drop across an external 50m sense resistor and an internal feedback circuit. The CC charge rate is set by the RSET pin. It can be calculated by the following formula: ICHARGE = 2500/R Where R is the value of the resistor connected to RSET. The charge current can range from 0.5A to 1.5A. The safety timer begins when CC mode is entered. If it expires during CC mode, the charger enters a fault state. If the current-sense feedback or RSET resistor is shorted, the charger clamps current at IOVERCURRENT.
Li+ Charger CC Operation Detailed Description
In CC mode, the CCCV charger regulates current by monitoring the voltage drop across the SNS resistor. The differential voltage measurement provides feedback that controls the switching of the high-side and low-side FETs. Inside the DS2731 CHG1 and CHG2 pins are a high-side p-channel MOSFET (Q1) and a low-side n-channel MOSFET (Q2). Q1 and Q2 alternate on and off, either supplying current to the load and inductor or providing a current loop for the inductor to supply the load. The inductor charges during Q1 ON and discharges during Q2 ON. The Q1 and Q2 switching is controlled by the voltage across RSNS.
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Cache-Memory Battery-Backup Management IC DS2731
IL IBATT
The MARGIN pin sets the CV threshold according to the following formula: VPK (CV Set Point) = 4.97V x R1/(R2 + R1) Where R2 is the resistor between STMR and MARGIN, and R1 is the resistor between MARGIN and ground. Voltage regulation can be set from 3.8V to 4.6V. If the safety timer expires during CV mode the charger enters the fault state. A fault that occurs in CV mode, once cleared, causes the charger to transition to done. Charge resumes if/when the battery voltage collapses to 95% (VDELTA) of the CV threshold.
IIN Q1 ON Q2 ON Q1 ON Q2 ON Q1 ON Q2 ON Q1 ON Q2 ON
ISWITCH(Q1) IBATT
Fault Conditions
There are several types of fault conditions that can occur. The precondition timer or safety timer can expire and the charger enters the fault state. This fault condition must be cleared by power cycling the part or toggling ENC. If the temperate exceeds the hot or cold limits, the charger enters fault. In the case of a temperature fault, charging resumes once the temperature returns to the normal operation range unless the fault occurs in CV mode. If a fault occurs in CV mode, the charger sees a charge termination condition because the current has dropped below 5% x ICHG. Once the fault condition is removed the charger transitions to done. The charger remains in the done state unless the cell voltage collapses below 95% (VDELTA) of the CV threshold.
ISWITCH(Q2) IBATT
Thermal Protection
Figure 5. Li+ Battery Charger CC Operation Characteristics
The current in the inductor is a combination of the current in Q1 and Q2. The voltage on the inductor is higher during Q1 ON than Q2 ON. This allows the current in the inductor to remain continuous because the powerin approximately equals the power-out.
Constant-Voltage (CV) Mode
CV mode is entered after CC mode when the battery voltage reaches the CV output threshold. Battery voltage is measured at the BATT+ pin. When the voltage reaches the CV threshold set by the MARGIN pin, regulation goes from CC mode to CV mode. Charge termination occurs when the current drops below 5% of the CC charge rate.
The charger circuitry has a shutdown feature that pauses charging if the internal die temperature exceeds 160C. Charging resumes after the temperature has cooled 20C below 160C. The charger circuitry is also equipped with a temperature choke point. If the die temperature reaches 100C, the CCCV charger begins to choke the current 133mA/C above 100C. The choke continues down to 0mA if the temperature continues to increase. These thermal-regulation features operate independent of the thermistor input.
Enable Charger
The ENC pin is an active-high input that enables the charger. When enabled, the DS2731 performs battery qualification and begins charging using the CCCV algorithm. Toggling ENC resets charge timers and clears fault conditions. Any time ENC is low, the DS2731 charging circuitry is disabled and the highside switch is guaranteed to be off. No current can flow from the battery to the VIN pin when the charger is off.
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Cache-Memory Battery-Backup Management IC
Safety Timer
The charger has a safety timer that controls the maximum length of time for a charge cycle. It is user selectable from 1 to 10 hours. If this timer expires and the battery has failed to reach the termination current, the charger enters the fault state and is latched off. Charging does not continue until either power is cycled or the ENC pin is strobed low and then high again. The timer does not start until CC mode is entered and continues through CV mode. Precharge mode is not included in the STMR. Timing Equation: 0.1647 x RSTMR = t (in seconds); RSTMR = R1 + R2 Where R1 is the resistor from MARGIN to ground and R2 is the resistor from STMR to MARGIN. tionality can be disabled by grounding the THM pin and charging is independent of temperature. During charging, if the voltage on the THM pin goes below VHOT volts, the charger pauses until the voltage rises above VHYS-HOT volts. Also, if the voltage on the THM pin goes above VCOLD volts, the charger pauses until the voltage falls below V HYS-COLD volts. All timers pause while charging is interrupted and resume when the temperature returns to the valid range. The charger enters the fault state when an overtemperature or undertemperature condition occurs. A 10k NTC thermistor is recommended for this pin.
DS2731
Charge Status Indicators
The CHARGE, FAULT, and DONE pins can be used as digital discretes or as LED drivers; they are open drain. When charging, the CHARGE pin is held low. When the charger detects a full battery/termination condition, ITERMINATE, the DONE pin goes low and the CHARGE pin goes high impedance. Any charging fault (overtemperature or expiration of the safety timer) causes the FAULT pin to flash at a 4Hz rate and the CHARGE and DONE pins go high impedance. The FAULT pin stays on solid, not flash, if the fault occurs in CV mode.
Thermistor Input
Battery temperature can be monitored using an external thermistor. The THM input goes to a comparator and is pulled up internally by a 10k resistor. The voltage on this pin must be above VHYS-HOT and below VHYS-COLD in order to start charging. Thermistor func-
Table 1. Thermistor Threshold
TEMPERATURE (C) THM THRESHOLD RATIO OF CBIAS THERMISTOR RESISTANCE (k ) 27.040 4.925 -- SEMITEC 103AT-2 0 45 -- FENWAL 197-103LAG-A01 173-103LAF-301 4 42 --
COLD HOT DISABLE
0.739 0.283 0.030
Table 2. Charge Status Indicator Description
CONDITION Precharge Battery Charged Fault Charger Disabled CHARGE PIN Low High-Z High-Z High-Z DONE PIN High-Z Low High-Z High-Z FAULT PIN High-Z High-Z Blinking High-Z -- (Done) 50% DF, 4Hz rate; low if fault occurs during CV mode. -- COMMENT
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Cache-Memory Battery-Backup Management IC DS2731
VTHM
VCOLD VHYS-COLD
VHOT-HYS VHOT
VENABLE VDISABLE THERMISTOR FUNCTIONALLY DISABLED TIME
CHARGING ENABLED
CHARGING DISABLED
NOTE: THIS GRAPH IS NOT MEANT TO REPRESENT A LOGICAL PROGRESSION OF TEMPERATURE OVER TIME BUT RATHER THE VOLTAGE THRESHOLDS AT WHICH CHARGING IS DISABLED.
Figure 6. Temperature Operation
Cache-Memory Battery-Backup Buck-Regulator Supply (2MHz PWM)
A 2MHz internal synchronous buck regulator is used to generate the appropriate cache-memory supply voltage. With careful inductor selection, high efficiencies can be achieved with this type of supply (see Figures 7a and 7b). The regulator has a user-selectable voltage range of 0.9V to 2.5V, and can supply up to 450mA. There is also a user-selectable LO_BATT threshold with a range of 2.5V to 3V. If the battery voltage drops
below this threshold, the regulator shuts down and the IC goes into a low-power state until system power is restored. The regulator can be disabled by the ENS pin during normal power conditions. The buck regulator is designed to supply enough current to power the cache memory during data retention/refresh mode. The regulator can be enabled during normal system power, but it cannot supply power to the cache memory during normal operating conditions. Note: The buck regulator and the charger should not run simultaneously.
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Cache-Memory Battery-Backup Management IC
Buck-Regulator Operation Overview
VREG is the feedback pin for the 2MHz PWM switching regulator cache-memory supply. The switching node uses this voltage reference feedback to regulate the output voltage to the value specified by DIV. The switching power-supply high-side and low-side FETs drive LX. The output inductor is connected to this node. During normal operation, the switching frequency observed on the LX pin is approximately 2MHz. The exact switching frequency and duty factor varies based on load and inductor selection. The SGND pin connects to the source of the internal low-side switch. This pin should be routed from the DS2731 to the negative terminal of the output capacitor. There are fast transient currents in this connection caused by the commutation of the body-drain diode of the low-side switch when the high-side switch turns on. Considerations should be taken during layout to minimize EMI. The buck regulator is equipped with an internal temperature-shutdown circuit that turns off the regulator if the circuit temperature reaches 165C. Regulation resumes once the temperature has cooled 15C below 165C.
DS2731
MEMORY BUCK EFFICIENCY 92.0 91.5 91.0 90.5 90.0 % EFFICIENCY 89.5 89.0 88.5 88.0 87.5 87.0 86.5 10 30 50 70 90 110 130 LOAD (mA) 150 170 190 210 230 250
NOTE: THE INDUCTOR USED FOR EFFICIENCY MEASUREMENT WAS 2.2H 20%. CURRENT RATING: 250mA for 30% INDUCTANCE DROOP AND 260mA FOR WIRE CSA LIMIT OF 300 CIRCULAR MILS PER AMP.
Figure 7a. Memory Buck Regulator Efficiency with 2.2H Inductor
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Cache-Memory Battery-Backup Management IC DS2731
LINE REGULATION vs. VBATT AT LOADS 1.79 1.78 1.77 VMEM (V) 1.76 1.75 1.74 1.73 1.72 2.8 3.6 VBATT (V) 20mA 250mA 4.2
Setting Memory Voltage and Low-Battery Shutdown
The cache-memory and low-battery shutdown voltages are set using a 1.25V reference and resistor-divider. The 1.25V reference is supplied at the REF pin. This pin cannot supply power for any system loads. In order to ensure that the voltage reference is not overloaded, a 1M total resistor-divider network is recommended.
Memory Voltage
The voltage on the DIV pin is the average DC voltage set point to which the cache-memory supply regulates. The cache-memory supply voltage can range from 0.9V to 2.5V and is set by the following formula: VDIV x 25/12 = VVREG
Low-Battery Shutdown
The voltage on the LO_BATT pin is compared to the prescaled battery voltage. The scale factor is 4.5:1. When the scaled battery voltage drops below the voltage on LO_BATT, the IC goes into quiescent-power mode. All circuitry is shut off and does not turn on again until the VBIAS voltage is stable and UVLO-REG is off. The low-battery voltage set point can be determined by the following formula: VLO_BATT x 4.5 = Low-Battery Voltage Set Point
Figure 7b. Memory Buck Regulator Line Regulation vs. Battery Voltage at Loads
IOCLP IOCDC IOCLN
PON
NON
PON
NON
PON
NON
PON
NON
Figure 8. Buck Regulator Overcurrent Switching
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Cache-Memory Battery-Backup Management IC
Layout
Due to high-frequency switching, high-current loops, and large-voltage switching, special consideration should be taken for layout of the DS2731 board in order to reduce EMI.
Power-Failure Switchover
During a power-failure event, the DS2731 can assume responsibility for supplying power to the cache memory using the backup battery. As long as the 2MHz internal synchronous buck regulator is enabled and the battery voltage is above LO_BATT, the buck regulator supplies power to the memory. During normal power the buck regulator runs off of the aux input voltage. The DS2731 monitors the aux input voltage for power failure. During a power-failure event, the DS2731 internally switches the buck-regulator supply to the battery backup. The battery is connected internally by a break-before-make switching mux. The break-before-make circuitry ensures that the battery is never connected to the 3.3V aux supply. The capacitor on the CIN pin provides power to the IC during switchover. If the buck regulator is disabled during normal power conditions, ENS must be driven low by the system when a loss of power is detected.
DS2731
CCCV Charger
The CCCV charger generates a high-current loop from VIN to CHG1 and CHG2 to CGND1 and CGND2. Also, large dV/dT is generated at CHG1 and CHG2 from the switching on and off of the 12V supply. These combine to generate magnetic and electric fields. To reduce these fields, the high-current loop should be made as small as possible. Traces should be routed point-topoint, as straight as possible, and a ground plane/shield should be used to isolate the noise from nearby components. Also, the trace width of the charge path should be sufficiently large enough to accommodate the high current. SNS and BATT+ should be connected as close as possible to the SNS resistor and BATT+ terminal for accurate current regulation and battery voltage measurements. The AGND pin is the analog reference connection. No charge current flows into AGND. It should be connected as close as possible to the negative terminal of the battery. This allows for a more accurate battery voltage measurement by avoiding any voltage drops caused by stray resistance in the high-current charge path.
Auxiliary Voltage
The aux switch monitors the aux power supply. In the system, this supply fails before the cache-memory power supply. When it crosses 2.93V, a comparator in the DS2731 activates the power multiplexer and switches the power source for the buck regulator from the aux power to the battery. This occurs as a break-beforemake operation to prevent current from flowing out of the battery into the aux supply.
Cache-Memory Buck Regulator
Even though the voltages and currents are not as high as the CCCV charger, care still needs to be taken during layout of the memory buck regulator. There are fasttransient voltages at LX. The fast-transient current loop is from CIN to LX to SGND. Again, the current loop should be routed as small as possible and ground shielding should be used to isolate the circuit.
Bypass/Holdup Capacitor
The bypass/holdup capacitor, connected to pin CIN, is sized to be able to support full input current to the switcher in the case where the ENS pin is low when the aux voltage falls below 2.93V. Since the power mux is break-before-make, the capacitor supplies power during the handover operation. Prior to the event, the capacitor is charged to 2.93V, and immediately afterwards it is connected to the battery voltage through the 1 mux switch. If power is restored, the conduction path between the battery and holdup capacitor is opened before the capacitor is connected to the 3.3V aux supply.
Enable Switcher
The buck regulator is enabled by the ENS pin. If the pin is low, the regulator turns on supplying power to the cache memory. The ENS pin should be driven low by the system when the cache memory has halted active processing and is in its data-retention/refresh mode.
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Cache-Memory Battery-Backup Management IC DS2731
12V DETECT POWER FAILURE 10V VOLTAGE
3.3V 2.93V
DETECT 3.3V FAILURE
VOLTAGE
ENS
T1
T2
T3 T4
TIME
Figure 9. Expected Scenario for Multiplex Switchover from Aux to Battery
Actions Occurring During Time Intervals
From T1 to T2: At T1, the power-failure signal occurs and the system must put the cache memory into its self-refresh mode. Then it must shut off the system cache supply. Between the time the system power supply is shut off and the ENS pin is driven low, the cache memory is powered from its local bypass capacitance. From T2 to T3: When the ENS pin goes low, the DS2731 buck regulator turns on and takes over regulation of the cachememory voltage. The power source for the DS2731's switcher during this interval is the 3.3V aux voltage.
From T3 to T4: At time T3, the DS2731 detects that the 3.3V aux supply is about to fail and activates the multiplexer. However, to prevent cross-connections between the 3.3V aux and the battery, the multiplexer is designed as break-beforemake. The interval T3-T4 is t BRK . During this interval the DS2731 switching supply uses the holdup capacitor on CIN as its power source. CIN must be sized so that it has enough capacity to hold up the regulator for tBRK. After T4: At T4, the multiplexer connects CIN to the battery's positive terminal. The regulator operates from the battery.
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Cache-Memory Battery-Backup Management IC
Reapplication of Power
This is essentially the reverse process from the powerloss sequence. Power is applied to the RAID card; the 12V and 3.3V buses turn on and become stable. The main cache-memory power supply turns on but the power MOSFET that connects the cache to the cachepower supply remains off. The cache-backup supply in the DS2731 automatically switches from the battery source to the 3.3V bus when the 3.3V bus goes above 2.93V. The system then disables ENS and enables the cache's power MOSFET, connecting the cache to the main cache power supply. Enough bulk storage capacitance must be available at the cache to hold up during this switchover time. The memory is now ready to exit from autorefresh mode (IDD6 for DDR2 memory) and resume full operation.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 28 TSSOP PACKAGE CODE -- DOCUMENT NO. 21-0108
DS2731
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Cache-Memory Battery-Backup Management IC DS2731
Revision History
REVISION NUMBER 0 1 REVISION DATE 11/07 1/09 DESCRIPTION PAGES CHANGED
Initial release. Corrected part numbers in the Ordering Information table.
-- 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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